The core of the system was a hybrid, distributed control architecture.

Topic 0 - BOM

- For high-level, computationally intensive tasks such as Reinforcement Learning (PPO policy) and the Sim2Real pipeline, I selected the NVIDIA Jetson Nano for its onboard GPU processing capabilities.

- For low-level, high-frequency control of the 7-DOF joints, each joint actuator was paired with a dedicated STM32F4 series microcontroller selected for its high-performance ARM Cortex-M4 core, enabling a rapid control loop frequency of over 1 kHz.

Topic 1 - Protocol Communication

All microcontrollers and the Jetson Nano communicated over a daisy-chained CAN-EtherCAT protocol.

- This choice was critical: EtherCAT provides deterministic, hard real-time communication with a jitter of under 1 µs and a network update rate of up to 30 kHz, which is essential for synchronized gait and balance control. This bypassed the non-deterministic latency issues of standard Ethernet. The power system was a meticulously designed hierarchy.

For the CAN-EtherCAT bus, I used controlled-impedance traces (typically 50-ohm) and implemented a differential pair routing strategy.

This minimized signal reflections and common-mode noise, ensuring the sub-microsecond jitter was maintained. I used length-matching techniques for the differential pairs with a tolerance of less than 1 mm to prevent skew and ensure signal integrity at the high communication speeds.

Topic 2 - Power Integrity

I used a main 48V bus, distributing power to each joint's local power supply. At each joint, a high-efficiency buck-boost converter (e.g., LM5176) supplied a stable 12V rail for the microcontroller and sensor suite. To handle instantaneous torque demands (peak currents of up to 20A per joint during gait transitions), each joint's power circuit included a local capacitor bank of 4700µF, designed to minimize voltage droop to under 5% during transient loads.

Topic 3 - Validation at Logic Level

Pre-fabrication, I used SystemVerilog to conduct RTL Verification (UVM) for the core digital logic and performed mixed-signal simulations using Cadence EDA to validate the embedded compute module's design, ensuring signal integrity on high-speed traces.

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MY FINALIZED EE DESIGN STRATEGY: Layout of main PCB block diagram

- The Jetson Nano and the STM32 microcontrollers were placed on the digital side of the board.

- The analog-to-digital converters (ADCs) for sensor feedback were placed on the analog side,

with a "moat" or split ground plane to prevent digital switching noise from contaminating the analog signals.

A single-point ground connection was used to merge the planes and prevent ground loops.

A primary design challenge for the humanoid robot was managing high-power, high-frequency signals in a compact, motion-constrained environment. The PCB was a multi-layered board (6-8 layers) with a high-density interconnect (HDI) structure, using blind and buried vias to achieve the required component density.

- A critical aspect of the PCB layout was the isolation of the high-power motor driver circuits from the sensitive control and communication circuitry. I used a dedicated, low-impedance power plane and a separate ground plane for the motor drivers to handle the large current surges and prevent noise from propagating. This required a calculated separation of at least 15mm from the main digital control circuits.

EXPLANATIONS

Actuation & Control Loop Determinism:

Question: Why did you choose EtherCAT over standard CAN or EtherNET/IP? Can you prove the sub-microsecond jitter claim and its impact on motion control?

Rationale: Standard protocols like EtherNET/IP are non-deterministic, with variable latency that would make synchronized, high-frequency joint control impossible. CAN is deterministic but lacks the bandwidth for a high-DOF system. EtherCAT's distributed clock mechanism guarantees a synchronization jitter of less than 1 µs, which is critical for a dynamically stable bipedal gait.

Power System Integrity:

Question: How did you size the local capacitor bank for each joint? Can you prove the voltage droop will remain below 5% during a peak torque event?

Rationale: The rapid, high-current draw of the BLDC motors during dynamic movements can cause a significant voltage droop, which could reset the microcontroller. The capacitor bank must be large enough to supply this instantaneous power. The 5% tolerance ensures the microcontroller's minimum operating voltage is maintained.

((THEORETICAL MODELS))

The required capacitance (C) to limit voltage droop (ΔV) for a given transient load (ΔI) over a period (Δt) is calculated by the equation:

C= ( ΔI⋅Δt ) / ΔV

​

CAPACTIOR BANK SIZING DESIGNING

For a peak current surge of ΔI=20A and a required response time of Δt=100μs (a typical gait cycle event), with a maximum allowable voltage droop of ΔV=5% (e.g., 48V⋅0.05=2.4V), the required capacitance is:

C= (20A⋅100⋅10^-6 sec) / 2.4V ≈833μF

To provide a sufficient margin of safety, a 4700µF capacitor bank was selected, exceeding the calculated requirement by over 5x.

The local 4700µF capacitor bank was sized to handle this transient load and prevent voltage droop. My initial calculation yielded a theoretical need for 833μF. However, this is an ideal value.

Power System Voltage Droop:

Now, a proper design must account for the capacitor's Equivalent Series Resistance (ESR) (ESR is the resistive voltage drop), which causes an instantaneous voltage drop. The total voltage droop is given by:

ΔV_total = (I_surge ⋅ ESR) + ( (I_surge * ⋅Δt) / C)

​

Since votlage drops occur due to rapid current change or trace inductance (V_L = L* dI/dt) and in knowing capacitors' valus degrade by time, using a large capacitor bank, I can ensure I have selected a component with a very low ESR, ensuring the voltage droop was kept well under the 5% tolerance, even during a full 20A surge.

POWER INTEGRITY

~~ Why did I choose 48V? ~~

The use of a main 48V bus was a deliberate choice to minimize resistive power losses, which are governed by the equation:

P_loss =I^2*R

= by increasing the voltage by a factor of four from a *typical 12V system*, we *reduced the current* by a factor of four, which in turn *reduced the power loss* by a factor of 16.

----> this allowed for the use of *lighter gauge wires*, a key factor in the robot's SWAP-C optimization.

~~ Why choose 20A? ~~

The 20A peak current for each joint was not a guess. It was a *direct result of the mechanical design and simulations*.

The "peak torque required by the gait model" (from the FEA) was used to calculate the necessary current:

I_peak = T_peak / k_t

where T_peak is **maximum required torque that should be producable**

k_t is Motor Torque constant (always same per motor type): which is 1.25 Nm/A for BLDC custom motors

so if each joint needs 25 Nm (from FEA).

then I_peak = 25Nm/1.25 Nm/A =20 A

PRESERVE HOW

Power integrity was a multi-layered design strategy.

1) Primary Filter: The main power supply was a high-quality unit --> had built-in filtering.

2) Secondary Filter: The local 4700µF capacitor bank at each joint acted as a low-frequency filter to handle large transient loads.

3) Tertiary Filter: Finally, ceramic decoupling capacitors were placed as close as possible to the power pins of every IC (e.g., the STM32). This is a best practice from The Art of Electronics to filter out high-frequency noise and prevent voltage drops at the IC itself, which would otherwise lead to a **brownout reset**

--> The decoupling capacitors provide a local reservoir of charge that can respond to these rapid changes in current, minimizing the voltage drop at the IC's power pin.

Choosing Network Procotol:

The choice of EtherCAT was critical because a walking robot requires hard real-time communication with minimal jitter for synchronized gait and balance.

- Standard Ethernet uses a collision detection protocol, which introduces non-deterministic latency. EtherCAT, an IEEE 1588 (PTP) compliant protocol, uses a master/slave architecture and a passing-packet methodology to achieve a jitter of under 1 µs and a network update rate of up to 30 kHz --> this deterministic behavior ensures all seven joints receive their new commands at the exact same time, preventing asynchronous movements that would lead to a fall.

= To preserve this sub-microsecond performance, the physical layer was meticulously designed. The use of controlled-impedance traces and differential pair routing was non-negotiable.

PHY LAYER:

TThe high-speed CAN-EtherCAT bus, with its sub-microsecond jitter, is only as good as its physical implementation.

The use of controlled-impedance traces and differential pairs was critical to prevent signal integrity issues.

--> Signal reflections occur when the load impedance (Z_L) does not match the characteristic impedance (Z0) of the trace.

The key principle here is to minimize signal reflections, which are governed by the reflection coefficient (ρ):

ρ= (Z_L - Z0) / (Z_L + Z0)

where Z_L is Controlled (load) impedance.

and Z0 is the characteristic impedance of the trace (instrinsic constant)

1) By designing the traces to have a characteristic impedance of 50 Ω (the standard for EtherCAT differential pairs per eaech linee) and terminating the bus with a matching resistor, we drove ρ to zero, eliminating reflections that would otherwise corrupt the signal and cause jitter.

- This is "matching the line impendance to the load" (Controlled Impedance) & allowing me to maintain the sub-microsecond jitter.

2) Furthermore, length-matching the differential pairs to under 1 mm was done and is crucial to prevent *signal skew*, a timing mismatch between the two signals.

Skew would have degraded the signal (craeeting timing errors) and increased the Bit Error Rate (BER), which would lead to dropped packets and gait instability.

--> this is "Differential Pair Routing": This technique was used to actively cancel out common-mode noise, which is any electrical noise that affects both lines of the pair equally.

The receiver only looks at the voltage difference between the two lines, rejecting the common-mode noise. This significantly improves the signal-to-noise ratio (SNR), a key metric for signal integrity. To ensure this, the differential pairs are length-matched

Broaden Networking

While the real-time control bypassed protocols like TCP/IP, my knowledge of them was crucial. The Jetson Nano's development environment used standard protocols for remote debugging (SSH), file transfer (SCP), and connecting to a ROS Master for monitoring. This shows an understanding of the entire networking stack, not just the real-time portion.

If can add more:

In a production-level system, a high-end robot might use a more powerful PCIe-based GPU module connected via a high-speed interconnect like NVLink. While my project's BOM choice of a Jetson Nano was based on SWAP-C (Size, Weight, and Power-Cost) constraints, understanding these high-end technologies proves I can scale the design to a more complex system. PCIe provides a high-speed link for data to flow from sensors to the GPU. NVLink would be used to connect multiple GPUs for even more intensive parallel processing.

PCB Layout:

~~Why a split ground plane? Why 6-8 layers?~~

The split ground plane, or "moat," was a fundamental design choice for mixed-signal isolation.

- Digital circuits, like the Jetson and STM32, generate *high-frequency switching noise* that can couple into the sensitive analog signals from sensors via the shared ground plane

This is known as "ground bounce" = can severely corrupt sensor readings.

Having a moat physically isolates the digital and analog ground planes, with a single-point connection --> preventing ground loops. This ensured the ADCs received a clean signal reference.

- The 6-8 layer PCB was a direct application of the SWAP-C (Size, Weight, and Power-Cost) protocol.

To achieve the required component density and *isolate signals in a compact form factor*, we needed dedicated layers.

Layers 1 & 6 (Top/Bottom): High-speed signal routing (e.g., EtherCAT traces).

Layer 2: Dedicated, low-impedance ground plane for the sensitive analog circuitry.

Layer 3: Power plane for the digital control circuits.

Layers 4 & 5: Dedicated, low-impedance power and ground planes for the high-current motor driver circuits.

= This separation **prevented high-current surges** from the motors from *propagating noise into the control circuitry*.

--> The physical separation of 15mm from the high-power circuits to the sensitive control circuitry was calculated to prevent EMI from radiating into the digital sections.

~~ How did we get 15mm as the seperation choicee from Power and Digtital?~~

15mm was calculated because EMI is huge issue in compact form factors like this. EMI is caused by rapid change in currnet (dI/dt), usually during switching like with MOSFETs. By Farday's Law of Induction, changing magnetic fields induces/triggers a voltage in a nearby conductive loop which can create noise.

Often here, high-power motor circuits acts as the aggrssor aka *source loop* and a narby seensitive (analog usually) signal trac on control circuitry acts as a *victim loop*.

=You want to seperate thee two with a disance (d) so that the induced voltage in the victim loop is below the noise margin of the digital logic

V_induced = - dϕ / dt

where ϕ is magntic flux, producede by magnetic field strength (H) and thee area (A = w*l) of the victim loop

ϕ=μ0 * μ_r * H*A

whree μ0 is permiability of freee space and μ_r is relativ prmaibilty of the meedium (1 for air aka *FR4*), A is width of trace times length of trace in qustion

If we assume MOSFET switching has a rise time of 100 nanosec before it tends to flip its switch (during Power) and a peak currnt of 20A is occuring,

dI/dt = peak current / rise time of a switch

20A/100^10-9 = 2*10^8 A/s

In general, 3.3V CMOS (digital) logic family has a known noise margin accetede before geetting corruptede in signal loss: 200mV

If assuming worse cases (so 10mm x 10mm as A), we use this equation for distanc btwen powr (analog) and digital logic gap on form factor:

d = [ (A*μ0*μ_r) / (2*pi) ] * [ (dI/dt) / V_induced ]

here, say if μ0*μ_r was 4*pi*10^-7, this is [ (100*10^-6 m^2)(4*pi*10^-7 H/m) / 2pi ] * [ (2*10^8 A/s) / (0.2V) ] = 20 mm.

Unless it is known that there is a split ground lane (layer 2) we keep this worst case scenario disancee.

If inded a split ground plane, plug in more precise area for bttr optimizd distance, here being 15 mm.

Use a mixed-signal oscilloscpe with a near-field probe to masure the magnetic field strength (H) radiation from the motor driver cirucits. This can help accutally knw th ral EMI signatur.

= I placed the probe at varying distances from the high-power traces and measured the induced voltage on a test trace.

The measurements confirmed that the 15mm separation, combined with the other mitigation techniques like the split ground plane, was sufficient to keep the induced noise voltage well below the acceptable limit under all operating conditions.

Cabling and Connecors: Choices

The cable gauges were selected based on the AWG (American Wire Gauge) standard and the ampacity ratings for the given current.

- For the 48V main bus, I used a gauge rated to carry >20A with a safety margin to prevent thermal issues.

- For the joint-level connections, which carry the full 20A surge, I used high-quality, high-current connectors like the XT60,

chosen for their *low resistance and secure locking mechanism* to prevent signal loss during motion

//reminder: your currnt is your killer, so the lower the current, the thinner your gauge size can be (SWAP-C!)

How did I connect the wires?

-The main power bus was wired in a star topology from the central power supply. This ensures that each joint received the same voltage and was not affected by the current drawn by other joints, *which would be a problem in a daisy-chain power bus*

-For sensors and lower-power components, a series or bus topology was used.

How did you not lose signal in Cable?

Signal integrity was preserved through the use of differential pair routing and proper termination, as discussed in section 2.

For low-level sensor signals, a shielded twisted pair was used to mitigate EMI *from the high-current motor drivers.*

Topic 0 - BOM & Linkage Mechanism

The robot's skeleton was CAD-CAM modeled with a focus on bio-inspired mechanics, precisely replicating human ligaments and joints.

Topic 1 - Ashby Plot

- The frame was machined from 6061-T6 aluminum, chosen for its excellent strength-to-weight ratio and machinability.

Topic 2 - Actuators Design Calculated

- All structural joints were designed with high-precision ball bearings and a zero-backlash drivetrain to ensure smooth, repeatable motion.

- Joint actuation was powered by custom BLDC motors paired with harmonic gear drives, with a calculated peak torque of 25 Nm per leg joint to support dynamic walking and climbing.

Topic 3 - Validation on Loading Amount

- I performed Finite Element Analysis (FEA) and Computational Fluid Dynamics (CFD) simulations in Comsol Multiphysics to validate the design's structural integrity under dynamic loading and to optimize thermal dissipation from the motors and electronics. This simulation data was crucial for proving the mechanical feasibility of the design before a single part was fabricated.

EXPLANATIONS

Structural Integrity & Thermal Dissipation:

Question: How did you validate that the 6061-T6 aluminum structure would not deform under dynamic loads? How was thermal dissipation from the motors modeled and verified to prevent overheating?

Rationale: The structure must withstand forces from a dynamic gait without compromising joint alignment. The thermal model is crucial to ensure the motor and electronics do not exceed their maximum junction temperatures, which would lead to a degradation in performance or catastrophic failure.

((THEORETICAL MODELS))

Motor Sizing & Torque Calculation:

The required torque (τ) for each joint was determined by the inertia (I) and angular acceleration (α) during a gait cycle.

τ = I ⋅ α

((CALCULATION))

Through Inverse Kinematics and gait simulation in IsaacSim, I calculated the peak torque requirement for each joint, ensuring the selected motor and harmonic gear drive could handle the load.

For a dynamic walking cycle, the peak knee joint torque was modeled at 25 Nm, with an angular velocity of 1.5 rad/s.

--> The selected motor-gearbox combination was a 48V BLDC motor with a 100:1 harmonic drive, providing a peak torque of 30 Nm, which provided a 1.2x safety factor.

1. Actuation Systems & The Drivetrain

The core of a walking robot is its ability to generate and control torque precisely. Our actuation system was designed from the ground up to achieve high torque density and zero backlash, two critical metrics for bipedal locomotion.

Actuator & Drivetrain Selection

We chose a combination of custom BLDC motors and harmonic gear drives.

--> BLDC motors were selected for their high power-to-weight ratio and efficiency, essential for a battery-powered device.

-> The harmonic gear drive was non-negotiable due to its zero backlash characteristic.

= Backlash, or "slop," in a conventional gear train would have introduced significant positioning errors and hysteresis, making high-precision control and a stable gait impossible.

Calculations: Torque and Gear Ratio

The size of the motors and gearboxes was not an estimate; it was a direct result of our dynamic load calculations.

Our FEA (Finite Element Analysis) simulations of a single-leg stance determined a peak dynamic torque requirement of T_peak =25 Nm per joint.

The motor itself generates a specific torque, T_motor, which is then amplified by the gearbox. The gear ratio, i, is the key to this mechanical advantage.

T_output =T_motor⋅i⋅η

where T_output is how much we want to / should be abel to prdouce (eg. 25 Nm, our goal)

and T_motor is how much actual torque is beeing proudced solely as per manufacturing spec for the motor itself aka "Nominal Torque"

- i is the gear ratio.

- η is the gearbox efficiency (typically ~90% for a harmonic drive, aka "0.9").

So by selecting a motor with a nominal torque of 0.5 Nm, we calculated the required gear ratio:

i = T_output / Tmotor*n

= i=(25 Nm) / (0.5Nm*0.9) ≈55.5

By *selecting an off-the-shelf harmonic gear drive* with a ratio of 60:1, this is proves our COTS gear driv can safetly produce our torqu for sur (bc >55.5, hence we have a safe margin).

2. Structural Components & Material Selection

The robot's frame was the foundation of its strength and lightweight design, a direct application of the SWAP-C (Size, Weight, and Power-Cost) protocol.

The Ashby Plot & Material Selection

I used an Ashby plot to scientifically select the best material for the frame. . This powerful tool allowed me to visually compare materials based on two key metrics: specific strength (σy/ρ) and specific stiffness (E/ρ).

Specific Strength: The strength-to-weight ratio, crucial for withstanding dynamic loads without adding unnecessary mass.

= (σy) / ρ

aka yield strength over density

Specific Stiffness: The stiffness-to-weight ratio, vital for resisting bending and maintaining the precision of the joints.

Based on the plot, 6061-T6 aluminum was the clear front-runner. It offered an excellent balance of specific strength, stiffness, and most importantly, machinability. This made it an ideal choice for our CAD-CAM manufacturing process and allowed us to rapidly prototype and iterate on the design.

3. Joint Design & Fatigue Analysis

The longevity and reliability of the robot were validated through a rigorous analysis of the stresses and potential for fatigue failure in the joints.

Mohr's Circle & Multiaxial Stress Analysis

In a dynamic gait, the joints experience a combination of axial, shear, and bending loads. The maximum stress is not a simple value; it is a complex state of multiaxial stress. To find the true maximum stress, I used Mohr's Circle on the data from our FEA simulation. . This allowed me to determine the principal stresses:

(σ1,σ2) = (σx+σy)/2 +- sqrt( ((σx+σy)/2)^2 + (τxy)^2)

​

where σ is x and y's normal sress (peripndicular to surface arae) and τxy is your shear stress (parllel to surfae arae)

We use this to find the maximum and minimum normal stresses (σ1) at a given point on the joint, to see for eaech joint if we have a solid safety factor or not.

Factor of Safety (FOS) and Fatigue Analysis

For a material with a yield strength of 300 MPa, and a maximum principal stress (σ

max) of 50 MPa from the FEA, our FOS was:

FOS= σ_yield / σ_max =

300 MPa/50 MPa =6

A factor of safety of 6 is an excellent margin of safety, accounting for manufacturing variations and unforeseen abuse.

However, a static FOS is not enough for a robot that will be running for years.

--> Then lastly you follow up I performed a fatigue analysis using the S-N curve for 6061-T6 aluminum. By simulating the cyclic loads experienced during a typical gait, I was able to estimate the service life of the components. The analysis showed that the joints would withstand well over 10^6 cycles of motion, far exceeding the product's expected lifespan.

4. Manufacturing & Geometric Tolerancing (GD&T)

Our design was not just a theoretical model; it was engineered to be manufacturable. I applied DFM (Design for Manufacturability) principles and used GD&T (Geometric Dimensioning and Tolerancing) to ensure proper assembly.

Tolerance Stack-up Analysis

The proper function of each joint relied on the precise fit between multiple components (e.g., bearings, shafts, housing). A tolerance stack-up analysis was performed to ensure the required clearance or interference was met, even in a worst-case scenario.

Worst-Case Tolerance Stack-up:

Max Gap=(Max Part A)+(Max Part B)−(Min Part C)

This analysis was crucial for ensuring the bearings were properly preloaded, which is vital for eliminating play and ensuring smooth, repeatable motion. All critical interfaces were defined using GD&T callouts on the drawings, ensuring the design intent was communicated clearly to the machinist.

5. Validation, Characterization, and Optimization

My design process was not linear; it was a cycle of design, simulation, and validation.

FEA (Finite Element Analysis): I used Comsol Multiphysics to model and validate the structural integrity of the frame and joints under dynamic loading. This allowed me to identify stress concentrations and optimize the design to eliminate them before a single prototype was machined.

CFD (Computational Fluid Dynamics): I used CFD to model the thermal dissipation from the high-power BLDC motors and electronics

- This simulation was critical for ensuring that the components remained within their operating temperature range and would not suffer from thermal throttling or premature failure.

Physical Prototyping and Validation: After fabrication, I used instruments like a CMM (Coordinate Measuring Machine) to verify that the parts met the GD&T specifications, a thermal camera (FLIR) to validate the CFD models, and a high-speed camera (OptiTrack) to capture gait motion and compare it to our simulation models.